VHSIC Hardware Description Language, aka VHSIC Hardware Description Language, is an actively used hardware description language created in 1983. VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.. Read more on Wikipedia...

36Years Old 1,975Users 33Jobs

Example code from the Hello World Collection:

--Hello World in VHDL

ENTITY helloworld IS
END helloworld;

ARCHITECTURE hw OF helloworld IS



END hw;

Example code from Linguist:

-- VHDL example file

library ieee;
use ieee.std_logic_1164.all;

entity inverter is
	port(a : in std_logic;
	     b : out std_logic);
end entity;

architecture rtl of inverter is
	b <= not a;
end architecture;

Example code from Wikipedia:

  wait until START = '1'; -- wait until START is high
  for i in 1 to 10 loop -- then wait for a few clock periods...
    wait until rising_edge(CLK);
  end loop;

  for i in 1 to 10 loop 	-- write numbers 1 to 10 to DATA, 1 every cycle
    DATA <= to_unsigned(i, 8);
    wait until rising_edge(CLK);
  end loop;

  -- wait until the output changes
  wait on RESULT;
  -- now raise ACK for clock period
  ACK <= '1';
  wait until rising_edge(CLK);
  ACK <= '0';

  -- and so on...
end process;

Trending Repos

repo stars description
ghdl 777 VHDL 2008/93/87 simulator

Last updated November 16th, 2019