SystemVerilog

SystemVerilog is an actively used programming language created in 2002. SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware verification language used to model, design, simulate, test and implement electronic systems. SystemVerilog is based on Verilog and some extensions, and since 2008 Verilog is now part of the same IEEE standard. It is commonly used in the semiconductor and electronic design industry as an evolution of Verilog.. Read more on Wikipedia...

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• SystemVerilog ranks in the top 10% of languages
• the SystemVerilog wikipedia page
• SystemVerilog first appeared in 2002
• file extensions for SystemVerilog include sv, svh, vh, header and file
• See also: verilog, vhdl, openvera, java, c, property-specification-language, axiom
• Have a question about SystemVerilog not answered here? Email me and let me know how I can help.

Example code from Linguist:

function integer log2;
  input integer x;
  begin
    x = x-1;
    for (log2 = 0; x > 0; log2 = log2 + 1)
      x = x >> 1;
  end
endfunction

Example code from Wikipedia:

class eth_frame;
   // Definitions as above
   covergroup cov;
      coverpoint dest {
          bins bcast[1] = {48'hFFFFFFFFFFFF};
          bins ucast[1] = default;
      }
      coverpoint f_type {
          bins length[16] = { [0:1535] };
          bins typed[16] = { [1536:32767] };
          bins other[1] = default;
      }
      psize: coverpoint payload.size {
          bins size[] = { 46, [47:63], 64, [65:511], [512:1023], [1024:1499], 1500 };
      }

      sz_x_t: cross f_type, psize;
   endgroup
endclass

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