VHSIC Hardware Description Language, aka VHSIC Hardware Description Language, is an actively used programming language created in 1983.
- VHSIC Hardware Description Language ranks in the top 5% of languages
- the VHSIC Hardware Description Language wikipedia page
- VHSIC Hardware Description Language first appeared in 1983
- See also: verilog, ada, pascal, vhdl-ams, property-specification-language, isbn
- I have 80 facts about VHSIC Hardware Description Language. just email me if you need more.
Example code from the Hello World Collection:
--Hello World in VHDL ENTITY helloworld IS END helloworld; ARCHITECTURE hw OF helloworld IS BEGIN ASSERT FALSE REPORT "HELLO, WORLD!" SEVERITY NOTE; END hw;
Example code from Linguist:
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
Example code from Wikipedia:
process begin wait until START = '1'; -- wait until START is high for i in 1 to 10 loop -- then wait for a few clock periods... wait until rising_edge(CLK); end loop; for i in 1 to 10 loop -- write numbers 1 to 10 to DATA, 1 every cycle DATA <= to_unsigned(i, 8); wait until rising_edge(CLK); end loop; -- wait until the output changes wait on RESULT; -- now raise ACK for clock period ACK <= '1'; wait until rising_edge(CLK); ACK <= '0'; -- and so on... end process;Edit
Last updated February 11th, 2019