SystemVerilog is an actively used programming language created in 2002.

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Example code from Linguist:

function integer log2;
  input integer x;
  begin
    x = x-1;
    for (log2 = 0; x > 0; log2 = log2 + 1)
      x = x >> 1;
  end
endfunction

Example code from Wikipedia:

class eth_frame;
   // Definitions as above
   covergroup cov;
      coverpoint dest {
          bins bcast[1] = {48'hFFFFFFFFFFFF};
          bins ucast[1] = default;
      }
      coverpoint f_type {
          bins length[16] = { [0:1535] };
          bins typed[16] = { [1536:32767] };
          bins other[1] = default;
      }
      psize: coverpoint payload.size {
          bins size[] = { 46, [47:63], 64, [65:511], [512:1023], [1024:1499], 1500 };
      }

      sz_x_t: cross f_type, psize;
   endgroup
endclass
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Last updated February 11th, 2019